1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and to a method for generating a control signal therefor.
2. Related Art
FIG. 2(a) is a circuit diagram showing prior art. In this circuit, as shown in FIG. 2(b), a timer counter 10 performs counting operation in synchronization with a counting clock signal CK, a read buffer 20 reading in the value of the timer counter 10 in synchronization with a read clock signal RCK. On the rising edge of the counting clock signal CK, the timer counter 10 performs a counting operation.
A flip-flop 9 captures an inverted read strobe signal RDST, in synchronization with the counting clock signal CK. The output signal 9A of the flip-flop 9 and the counting lock signal CK are input to an AND circuit 30, and on the rising edge of the read clock RCK, which is the output from the AND circuit 30, a read buffer 20 captures the value of the timer counter 10. That is, when the read strobe signal RDST is 0, the read buffer 20 constantly captures the value of the timer counter 10, and when the read strobe signal RDST is 1, the read buffer 20 value is not updated.
As shown in FIG. 2(b), in the case in which the output signal 9A of flip-flop 9 is delayed, the read clock signal RCK rises, resulting in capture of data, and hindrance of the prescribed operation. For this reason, the counting clock signal CK is delayed by a delay circuit 40 provided in the clock line, and the read clock signal RCK is generated, so as to output to a read data bus 50 a properly established value of the read buffer 20.
In this case, however, because of the delay circuit 40, analysis using a static analysis tool becomes difficult.
FIG. 3(a) is an example of another circuit of the prior art, which is disclosed in Japanese Unexamined Patent Publication (KOKAI) No.2-7284.
In this case of this circuit, as shown in FIG. 3(b), if a period of a read strobe signal is shorter than that of one clockxcfx86, a glitch 50 occurs, so that this glitch acts as a read clock, resulting in unwanted data capture at the timing indicated by the arrow, this representing faulty operation.
Accordingly, it is an object of the present invention, in order to improve on the above-noted drawbacks of the prior art, to provide a novel semiconductor integrated circuit and method for generating a control signal therefor, which can be statically analyzed, and wherein faulty operation does not occur even if a period of read strobe signal is shorter than that of one clock.
In order to achieve the above-noted objects, the present invention has the following basic technical constitution.
Specifically, the first aspect of the present invention is a semiconductor integrated circuit in which data of a logic circuit which operates by an internal clock signal is read into a read buffer, using a readout clock signal that is not synchronized to the internal clock signal, comprising a selector, which selects either an inverted signal or a non-inverted signal, based on the condition of a read strobe signal that gives an instruction for readout of data in the logic circuit into the read buffer, a first flip-flop circuit, which latches a signal selected by the selector at a timing of the internal clock signal, and outputs a latched signal to the selector, a second flip-flop circuit, which shifts an output signal of the first flip-flop circuit at a timing of the internal clock signal, and an exclusive-OR circuit, which takes an exclusive OR of the output signal of the first flip-flop circuit and an output signal of the second flip-flop circuit, an output signal of the exclusive-OR circuit serves as the readout clock signal of the read buffer.
In the second aspect of the present invention, the output signal of the first flip-flop circuit is input to one terminal of the selector, and an inverted signal of the output signal of the first flip-flop circuit is input to another terminal of the selector.
The third aspect of the present invention is a control signal generating method for a semiconductor integrated circuit in which data of a logic circuit which operates by an internal clock signal is read into a read buffer, using a readout clock signal that is not synchronized to said internal clock signal, comprising: a first step of generating a pulse signal that is synchronous with the internal clock signal, when a read strobe signal is not giving an instruction or readout of data in the logic circuit to the read buffer, and of stopping to generate the pulse signal, when the read strobe signal gives an instruction for readout, a second step of shifting the pulse signal generated by the first step by one clock, in synchronization with the internal clock signal, and a third step of taking an exclusive OR of the signal generated by the first step and a signal generated by the second step, and using the resulting signal as the readout clock signal.